FPGA Verification Engineer
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About this role
Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
ABOUT THE TEAM
The Anduril Imaging team develops state-of-the-art imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies. The team is heavily involved in utilizing computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.
ABOUT THE JOB
The Imaging team is seeking a FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.
WHAT YOU’LL DO
• Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
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